1. Field of the Invention
This invention relates generally to data transfer operations between computer devices. In particular, the invention relates to methods of writing data to registers which control data transfer operations between devices in a computer system.
2. Description of the Related Art
The host processor of a computer system fetches and executes instructions which may cause the host processor to transfer data between the memory, a central processing unit (CPU) and an arithmetic and logic unit (ALU) or to initiate input/output (I/O) data transfer operations with I/O devices or peripherals external to the host processor. The computer system typically includes at least one controller which acts as the communications intermediary between the processor and one or more I/O subsystems, which may each contain one or more external I/O devices or peripherals. As a result transfer operations may not be optimized, and the wait time for processing data transferred through the computer system may be unnecessarily lengthened. The controller may be contained in a bridge, such as an I/O Controller Hub (ICH) available from Intel Corporation of Santa Clara, Calif., provided to interface with and buffer transfers of data between various computer devices.
The advanced technology attachment standard, frequently written as AT attachment (ATA) or integrated drive electronics (IDE), is commonly used for power and data signal interface communications between a host processor and a storage device. This set of standards is produced by Technical Committee T13 (www.t13.com) of the National Committee on Information Technology Standards (www.NCITS.org), Washington, D.C. The AT Attachment Interface for Disk Drives (ANSI X3.221-199×) is a disk drive interface standard that specifies the logical characteristics of the interconnecting signals as well as the protocols and commands for the storage device operation. This standard permits compatibility between host system products and storage device products that comply with the standard, even where these products are produced by different manufacturers.
An IDE controller is conventionally located between any IDE storage device (such as a hard disk drive) and the host processor. It serves as a translator to facilitate C(PU/IDE device communications over each I/O cycle. For example, on receiving an initialization command from the host processor, the IDE interface controller presents the command into something the downstream IDE device will understand, i.e. that the IDE device can handle, and sends this command to the attached IDE device. On receiving the converted command, the IDE device processes the command and sends back a completion notification to the processor through the IDE interface controller. This conventional I/O cycle from command sent to completion notification is a single task-file register access that may take approximately 1.2 microseconds (μs—one millionth (10−6) of a second).
Conventionally, the host processor dedicates a block of its processing time to the initialization of a peripheral, such as an IDE storage device. During this peripheral initialization dedication time, the host processor is prevented from performing other processing functions and thus its performance is slowed down. Furthermore, the performance of a bridge or a controller may be burdened by demands to access memory locations and control registers during data transfer operations. Conventional control registers usually offer only byte-level write control. Therefore, when software must write to a specific bit (or bits) of a byte in a control register, it must first read the byte, merge the bit (or bits) to be modified into the read byte, and then write the modified byte back to the register. See FIG. 3. For typical I/O and configuration registers, the processor is stalled approximately 1 microsecond (about 1,000 processor clocks) while performing this read-merge-write sequence (perhaps only to write a single bit). If the read-merge-write sequences are necessary for streamlining of the initialization command sequence, then they inherently prevent the sequence from being posted to the controller for the external I/O device or peripheral.